An automated tool for detecting ESD design errors

Author

Siha, S. ; Swaminathan, Hemalata ; Kadamati, Gopalarao ; Duvvury, Charvaka

Author_Institution

Texas Instrum. India, Bangalore, India

fYear

1998

fDate

6-8 Oct. 1998

Firstpage

208

Lastpage

217

Abstract

In this paper, we report the development of a unique software program that can detect ESD design and layout errors. The novel features of this tool include detection of sensitive spacing requirements to prevent parasitic current paths, compatibility of the protection devices to the circuits being protected, and critical bus resistance limits for protection efficiency. This tool has been successfully applied in ASIC designs.

Keywords

application specific integrated circuits; circuit CAD; electric resistance; fault currents; integrated circuit design; integrated circuit layout; integrated circuit reliability; software tools; ASIC design; ESD design error detection; ESD design errors; ESD layout errors; automated design tool; critical bus resistance; parasitic current paths; protection devices; protection efficiency; software program; spacing requirements; Application specific integrated circuits; Electrostatic discharge; Instruments; Product design; Protection; Qualifications; Reliability engineering; Silicon; Stress; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998

Conference_Location

Reno, NV, USA

Print_ISBN

1-878303-91-0

Type

conf

DOI

10.1109/EOSESD.1998.737040

Filename

737040