Reduction of QBD failures in a 0.5 μm BiCMOS process by reducing DC bias

Previously a non-classical failure mode was proposed for causing Qbd failure in a 0.5 μm BiCmos process. Machine parameters were used to minimise the failure rate. This provided protection against variations in machine performance which caused medium level fails (<50%) on a GOI monitor flow and product. However a new mechanism became apparent on one system which started to produce 100% failing monitors. This indicated a catastrophic breakdown within the chamber hardware, solutions were focused on two areas, firstly a root cause within the chamber hardware and secondly, the subject of this paper, process optimisation