Title :
45nm gate length Bulk/PD-SOI CMOS transistors with low gate leakage current for high speed and low power applications
Author :
Yang, C.K. ; Chen, T.F. ; Liang, C.S. ; Chen, T.J. ; Chang, T.C. ; Cheng, L.W. ; Lin, H.S. ; Li, G. ; Wu, D.Y. ; Chen, J.K. ; Chien, S.C. ; Sun, S.W. ; Cheek, J. ; Michael, M. ; Wu, D. ; Fisher, P. ; Wristers, Derick
Author_Institution :
United Microelectron. Corp., Hsinchu, Taiwan
Abstract :
45 nm gate length bulk/PD (partially depleted) SOI transistors, with high performance and ultra-low gate leakage, are presented in this paper. The nFETs and pFETs, operating at Vdd=1.2 V, possess driving currents of 1050 /spl mu/A//spl mu/m and 450 /spl mu/A//spl mu/m, as well as 980 /spl mu/A//spl mu/m and 490 /spl mu/A//spl mu/m at Ioff=20 nA//spl mu/m for bulk and PD-SOI devices respectively. The inversion gate leakage is only 1 A/cm/sup 2/ at Vdd=1.0 V. The robust device performance is quite suitable for both high speed and low operating power applications.
Keywords :
MOSFET; leakage currents; low-power electronics; silicon-on-insulator; 1.0 V; 1.2 V; 45 nm; bulk CMOS transistors; high speed transistors; inversion gate leakage; low power transistors; nFET; pFET; partially depleted SOI CMOS transistors; ultra-low gate leakage current; Annealing; Dielectrics; Gate leakage; Leakage current; MOSFETs; Plasma properties; Power dissipation; Silicon compounds; Sun; Tin;
Conference_Titel :
European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7999-3
DOI :
10.1109/ESSDERC.2003.1256902
