Title :
Optimisation of channel thickness in strained Si/SiGe MOSFETs
Author :
Kwa, K.S.K. ; Chattopadhyay, S. ; Olsen, S.H. ; Driscoll, L.S. ; O´Neill, A.G.
Author_Institution :
Sch.of Electr., Electron. & Comput. Eng., Newcastle upon Tyne Univ., UK
Abstract :
It is demonstrated from experimental I-V and C-V data, and confirmed by computer simulation, that strained Si/SiGe MOSFET performance severely degrades below a channel thickness of 7 nm. MOSFETs with strained Si channels of thickness 5 nm, 7 nm and 9 nm have been fabricated using a conventional high thermal budget process. The performance degradation is attributed to Ge diffusion through the strained Si layer, which causes a build up of gate oxide charge.
Keywords :
Ge-Si alloys; MOSFET; elemental semiconductors; optimisation; semiconductor materials; silicon; 5 nm; 7 nm; 9 nm; Ge diffusion; Si-SiGe; channel thickness optimisation; gate oxide charge; high thermal budget process; performance degradation; strained Si channels; strained Si/SiGe MOSFET; CMOS technology; Capacitance-voltage characteristics; Capacitive sensors; Fabrication; Germanium silicon alloys; MOSFETs; Silicon germanium; Substrates; Temperature; Thermal degradation;
Conference_Titel :
European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7999-3
DOI :
10.1109/ESSDERC.2003.1256923
