Demonstration of 20 Gbps digital test signal synthesis using SiGe and InP logic

Author

Keezer, D.C. ; Gray, C. ; Minier, D. ; Ducharme, P.

Author_Institution

Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2009

fDate

10-12 June 2009

Firstpage

1

Lastpage

5

Abstract

This paper demonstrates the signal performance obtained by combining data from two 10 Gbps SiGe serializers using a very high-speed, low-jitter InP exclusive-OR gate. The technique has been proven for lower-speed (i.e. les12.8Gbps) applications (Keezer et al., 2007). But its success at higher speeds depends upon tight control of timing and signal integrity. Relatively low-cost components are selected so that the method can be applied to test scenarios requiring many high-speed channels. Careful analysis of the demonstration circuit performance reveals the challenges, capabilities, and limitations of the method.

Keywords

Ge-Si alloys; digital signal processing chips; logic gates; logic testing; InP exclusive-OR gate; SiGe serializers; digital test signal synthesis; high-speed channels; Automatic testing; Circuit testing; Clocks; Electronic equipment testing; Germanium silicon alloys; Indium phosphide; Logic testing; Signal synthesis; Silicon germanium; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signals, Sensors, and Systems Test Workshop, 2009. IMS3TW '09. IEEE 15th International

Conference_Location

Scottsdale, AZ

Print_ISBN

978-1-4244-4618-6

Electronic_ISBN

978-1-4244-4617-9

Type

conf

DOI

10.1109/IMS3TW.2009.5158693

Filename

5158693