Influence of junction capacitance on SRAM SEU performance [MOSFETs]

Author

Xu, Y.Z. ; Pohland, O. ; Puchner, H.

Author_Institution

Res. & Dev., Cypress Semicond., San Jose, CA, USA

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

537

Lastpage

540

Abstract

Source and drain junction capacitance has been varied by utilizing different implant conditions for the MOSFETs to explore the possibility of improving SEU (single event upset) immunity of SRAM cells. It is found. that the junction capacitances of both the n/sup +//p-well and p/sup +//n-well can vary in a wide range. The resulting SEU FIT (failure in time) rate shows a significant reduction. HSPICE simulation indicates that critical charge of the SRAM cell increases by 5%. The reduction of funnel length due to the higher doping concentration in the source/drain area also improves SEU immunity.

Keywords

CMOS memory circuits; MOSFET; SRAM chips; alpha-particle effects; doping profiles; radiation hardening (electronics); CMOS technology; MOSFET implant conditions; SEU FIT rate; SEU immunity; SRAM cell SEU; SRAM cell critical charge; alpha particle induced failure rate; failure in time rate; funnel length reduction; junction capacitance; n/sup +//p-well; p/sup +//n-well; single event upset immunity; source/drain area doping concentration; source/drain junction capacitance; Alpha particles; CMOS technology; Circuit simulation; Doping; FETs; Implants; MOS devices; Parasitic capacitance; Random access memory; Single event upset;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7999-3

Type

conf

DOI

10.1109/ESSDERC.2003.1256932

Filename

1256932