DocumentCode
2443378
Title
ESD-implant effect on protection capability of NMOS structures
Author
Vashchenko, V.A. ; Concannon, A. ; Beek, M. Ter ; Hopper, P.
Author_Institution
Nat. Semicond. Corp., Santa Clara, CA, USA
fYear
2003
fDate
16-18 Sept. 2003
Firstpage
565
Lastpage
568
Abstract
The effect of the so-called ESD-implant was studied and clarified for the complex case of cascoded snapback NMOS structures suitable for 5 V tolerant I/O applications. The critical role of the ESD implant and epi-substrate resistivity on the local maximum temperature during the stress is clarified. Physical process and device numerical analysis was used to gain greater insight into these phenomena.
Keywords
MIS structures; electrostatic discharge; semiconductor device models; 5 V; ESD protection; ESD-implant effect; I/O circuits; NMOS structure protection capability; cascoded snapback NMOS structures; epi-substrate resistivity; stress induced local maximum temperature; Biological system modeling; CMOS technology; Circuit testing; Clamps; Conductivity; Electrostatic discharge; Implants; MOS devices; Protection; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on
Conference_Location
Estoril, Portugal
Print_ISBN
0-7803-7999-3
Type
conf
DOI
10.1109/ESSDERC.2003.1256939
Filename
1256939
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