H.264 Video Encoder Implementation on a Low-power DSP with Low and Stable Computational Complexity

This paper describes the implementation of an H.264 video encoder designed for use on a low-power DSP core (NEC Electronics Corporation´s SPXK6) for mobile equipment, which offers not only low computational complexity but small load fluctuation between average and peak load. In order to reduce the high degree of complexity that H.264 ordinarily requires, the encoder employs fast coding methods, including diamond motion searches, and fast decisions based on current-image smoothness as to which type of coding to employ. Further, to suppress increases in peak loads which would degrade real-time encoding performance, feedback-based control of computational complexity is used in motion estimation and intra/inter coding type decisions. On an SPXK6 DSP, the encoder performs H.264 baseline profile video coding at a QVGA (320times240 pixels) resolution of 15 fps, for an average load of 104 M cycle/sec, excluding memory access cycles, with the suppressed peak load increasing by only 20% over that of the average load