DocumentCode :
2443481
Title :
Hardware reduction methodology for 2-dimensional kurtotic fastica based on algorithmic analysis and architectural symmetry
Author :
Acharyya, Amit ; Maharatna, Koushik ; Al-Hashimi, B.M.
Author_Institution :
Pervasive Syst. Centre, Univ. of Southampton, Southampton, UK
fYear :
2009
fDate :
7-9 Oct. 2009
Abstract :
In this paper we propose a hardware reduction methodology through detailed algorithmic analysis and exploiting datapath symmetry for 2D Kurtotic Fast ICA. The relationship of the hardware saving with respect to input data frame-length and maximum iteration for convergence is also explored. An example architecture following the developed hardware reduction methodology consumes 3:55 mm2 silicon area and 27:1 muW @1 MHz at 1:2 V supply using 0:13 mum standard cell CMOS technology showing the effectiveness of the proposed methodology.
Keywords :
computer architecture; convergence of numerical methods; digital arithmetic; independent component analysis; iterative methods; 2D Kurtotic fastICA iteration; CMOS technology; algorithmic analysis; architectural symmetry; convergence; datapath symmetry; hardware reduction methodology; independent component analysis; silicon area; size 0.13 mum; Algorithm design and analysis; CMOS technology; Convergence; Covariance matrix; Floating-point arithmetic; Hardware; Independent component analysis; Signal processing algorithms; Silicon; Wireless sensor networks; BSS; FastICA; Low complexity; Low-power; Signal processing architecture;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems, 2009. SiPS 2009. IEEE Workshop on
Conference_Location :
Tampere
ISSN :
1520-6130
Print_ISBN :
978-1-4244-4335-2
Electronic_ISBN :
1520-6130
Type :
conf
DOI :
10.1109/SIPS.2009.5336227
Filename :
5336227
Link To Document :
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