Coherent interconnect/substrate modeling using SPACE - an experimental study

The functionality of modern ICs increasingly suffers from substrate noise. Digital transistors switching at high frequencies are known to induce substrate noise through their bulk contacts. In addition, interconnects carrying aggressive, high-frequency signals are known to induce substrate noise through their capacitive coupling with the substrate. In this paper, we describe how our layout-to-circuit extractor SPACE builds a coherent interconnect/substrate model from a layout. The result is a comprehensive circuit model which can immediately be simulated by a regular circuit simulator. We evaluate our modeling approach by extracting a ring-oscillator layout and simulating the resulting circuit with HSPICE. We have done extractions, under varying conditions; the simulation results give practical insight into relevant substrate noise phenomena.