Title :
A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding
Author :
Vogt, Timo ; Wehn, Norbert
Author_Institution :
Microelectron. Syst. Design Res. Group, Kaiserslautern Univ.
Abstract :
Future mobile and wireless communications networks require flexible modem architectures with high performance. This paper presents a dynamically reconfigurable application specific instruction set processor (dr-ASIP) for the application domain of channel coding in wireless communications systems: FlexiTreP. It features Viterbi and Log-MAP decoding for support of binary convolutional codes and binary as well as duobinary turbo codes. The FlexiTreP can support more than 10 current wireless communication standards. Furthermore, its flexibility allows for adaptation to future systems. It consists of a specialized pipeline and a dedicated communication and memory infrastructure. Simulation and synthesis results obtained for Log-MAP and Viterbi applications demonstrate maximum throughput of 200 and 133 Mbps, respectively
Keywords :
Viterbi decoding; application specific integrated circuits; binary codes; channel coding; convolutional codes; maximum likelihood decoding; radiocommunication; turbo codes; 133 Mbit/s; 200 Mbit/s; FlexiTreP; Log-MAP decoding; Viterbi decoding; application specific instruction set processor; binary convolutional codes; channel coding; dedicated communication; duobinary turbo codes; dynamically reconfigurable ASIP; memory infrastructure; specialized pipeline; wireless communications system; Channel coding; Communication standards; Convolutional codes; Decoding; Modems; Pipelines; Throughput; Turbo codes; Viterbi algorithm; Wireless communication;
Conference_Titel :
Signal Processing Systems Design and Implementation, 2006. SIPS '06. IEEE Workshop on
Conference_Location :
Banff, Alta.
Print_ISBN :
1-4244-0382-0
Electronic_ISBN :
1520-6130
DOI :
10.1109/SIPS.2006.352570
