Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks

Author

Kim, Daewoong ; Cha, Kilhyung ; Choi, Soonwoo ; Chae, Soo-Ik

Author_Institution

Electr. Eng. & Comput. Sci. Dept., Seoul Nat. Univ., Seoul, South Korea

fYear

2009

fDate

7-9 Oct. 2009

Firstpage

173

Lastpage

178

Abstract

A multi-core platform for high-performance video applications is proposed that contains multiple RISC clusters. Each cluster, which contains up to four cores and exploits thread-level parallelism, is allocated for a function block and connected to other clusters through two communication networks: one for control transfer and the other for data transfer. As an example, several mapping results of the H.264/AVC high profile 720 p decoder to the proposed platform are presented. According to the experimental results, we found that this platform is suitable for implementing a multi-standard video codec.

Keywords

decoding; parallel architectures; reduced instruction set computing; video codecs; video coding; H.264/AVC high profile 720 p decoder; configurable high-performance video platform; control networks; data transfer; multiple RISC clusters; multistandard video codec; thread-level parallelism; Application software; Automatic voltage control; Bandwidth; Communication networks; Communication system control; Decoding; Hardware; Parallel processing; Reduced instruction set computing; Streaming media; Multi-core platform; RISC cluster; communication networks; hardware operating system kernel;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2009. SiPS 2009. IEEE Workshop on

Conference_Location

Tampere

ISSN

1520-6130

Print_ISBN

978-1-4244-4335-2

Electronic_ISBN

1520-6130

Type

conf

DOI

10.1109/SIPS.2009.5336247

Filename

5336247