DocumentCode
2443903
Title
High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications
Author
Yuan, Bo ; Li, Li ; Wang, Zhongfeng
Author_Institution
Nanjing Univ., Nanjing, China
fYear
2009
fDate
7-9 Oct. 2009
Firstpage
179
Lastpage
184
Abstract
In current high-speed communication and storage systems, the increasing demand for providing flexible Reed-Solomon (RS) decoding solutions to multi-mode applications has created the desire of universal RS decoders. In this paper, we present a high-speed area-efficient versatile RS decoder architecture based on recursive degree computationless modified Euclidean (rDCME) algorithm. Targeting at different practical applications, the proposed architecture is developed into two universal RS decoder designs. Arithmetic modification to Montgomery multiplication is exploited for the reduction of area. Compared with existing works, the proposed configurable designs can deliver higher data rate with relatively lower hardware complexity, thus they are good candidates for high-speed multi-mode applications.
Keywords
Reed-Solomon codes; VLSI; decoding; multiplying circuits; Montgomery multiplication; Reed-Solomon decoder design; VLSI; arithmetic modification; recursive degree computationless modified Euclidean algorithm; Arithmetic; Computer architecture; Decoding; Digital communication; Error correction codes; Galois fields; Hardware; Reed-Solomon codes; Throughput; Very large scale integration; Reed-Solomon (RS) codes; VLSI architecture; degree computationless; modified Euclidean algorithm; versatile;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems, 2009. SiPS 2009. IEEE Workshop on
Conference_Location
Tampere
ISSN
1520-6130
Print_ISBN
978-1-4244-4335-2
Electronic_ISBN
1520-6130
Type
conf
DOI
10.1109/SIPS.2009.5336248
Filename
5336248
Link To Document