Evaluating SoC Network Performance in MPEG-4 Encoder

Some previous theoretical studies imply that mesh and other topologies outperform bus as a system-on-chip (SoC) interconnection. This paper shows how bus performs in a real implementation. We measure and analyze heterogeneous IP block interconnection (HIBI) bus for a multiple clock domain, multiprocessor system-on-chip (MPSoC) with an MPEG-4 video encoding application on FPGA. The system is benchmarked with seven different bus clock frequencies and four buffer sizes. A custom hardware monitor is used for the measurements. It is shown that the bus performance is adequate with significantly lower clock frequencies (5 MHz) than other components of the MPSoC (50-100 MHz). Based on the measurements, an estimate for the required bus and CPU frequencies for larger image formats and increased frames/s is shown. In contrast to the theoretical studies, the estimate shows that the bus is still a strong candidate for the SoC interconnection, because it is not the performance-limiting factor