Title :
Background light effect of a dynamically reconfigurable vision-chip architecture
Author :
Moriwaki, Retsu ; Watanabe, Minoru
Author_Institution :
Electr. & Electron. Eng., Shizuoka Univ., Shizuoka, Japan
Abstract :
Recently, demands for implementation of a high-speed image recognition function onto autonomous vehicles and robots, that is superior to that of the human eye, have been increasing. To date, analog-type vision chips and digital vision chips have been developed. Nevertheless, even now, realizing such high-speed real-time image recognition operation is extremely difficult because the template information transfer rate and template matching operation cycle reach the order of Petapixel/s. Therefore, to accommodate template matching operations that can be executed at rates greater than Petapixel/s, a dynamically reconfigurable vision-chip architecture has been developed in which a holographic memory technique is introduced to current VLSI technology. However, the dynamically reconfigurable vision-chip architecture must receive image information in addition to configuration context information. At such a time, a salient concern is that image information light might reduce the retention time of photodiode memories on a dynamically reconfigurable vision-chip. This paper therefore clarifies that the background light does not affect the photodiode memories on a dynamically reconfigurable vision-chip architecture.
Keywords :
VLSI; computer vision; digital signal processing chips; holographic storage; image matching; mobile robots; photodiodes; reconfigurable architectures; Petapixels; VLSI technology; analog-type vision chips; autonomous robots; autonomous vehicles; background light effect; configuration context information; digital vision chips; dynamically reconfigurable vision-chip architecture; high-speed image recognition function; high-speed real-time image recognition operation; holographic memory technique; human eye; image information light; photodiode memory; template information transfer rate; template matching operation cycle; template matching operations; Silicon; Dynamically reconfigurable devices; Field Programmable Gate Arrays; Vision chips;
Conference_Titel :
System Integration (SII), 2010 IEEE/SICE International Symposium on
Conference_Location :
Sendai
Print_ISBN :
978-1-4244-9316-6
DOI :
10.1109/SII.2010.5708363