Automatic Generation of Programmable Parallel CRC & Scrambler Designs

In this paper, we present an EDA tool for automatic generation of parallel CRC and parallel scrambler designs subject to different generator polynomials and parallel processing rates. The base architecture is derived from a state space transform scheme with fully pipelined pro- and post-processing blocks and the critical path is limited to 1 XOR delay only. The maximum input data width for CRC and scrambler designs are 64 and 32, respectively. It can also support the processing of data sequence length not an integral multiple of the parallel input width. Synthesis results indicate that for parallel CRC designs the maximum working frequency under UMC 0.18 mum process is 265.6 MHz and the maximum data rate is 17 Gbps. For parallel scrambler designs, the corresponding numbers are 375 Mhz and 12 Gbps