Title :
Estimation and optimization of delay in popular CMOS logic styles
Author :
Shams, Maitham ; Elmasry, Mohamed
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Abstract :
This paper presents a unified model for delay estimation in various CMOS logic styles. It also derives closed-form optimal transistor sizing formulas for minimizing the delay in each logic style. The paper demonstrates the use of these formulas for delay optimization in mixed logic-style CMOS circuits. Mixing CMOS logic styles in a circuit has the potential of improving performance and reducing energy dissipation and area.
Keywords :
CMOS logic circuits; circuit optimisation; delay estimation; integrated circuit design; logic design; logic gates; minimisation of switching nets; CMOS logic styles; DCVSL; PTL; closed-form optimal transistor sizing formulas; delay estimation; delay minimization; delay optimization; mixed logic-style CMOS circuits; pass-transistor logic; unified model; CMOS logic circuits; Delay estimation; Energy dissipation; Logic programming; MOS devices; MOSFETs; Mathematical programming; Semiconductor device modeling; Switches; Voltage;
Conference_Titel :
Microelectronics, 2001. ICM 2001 Proceedings. The 13th International Conference on
Print_ISBN :
0-7803-7522-X
DOI :
10.1109/ICM.2001.997484
