Title :
Binary division algorithm and implementation in VHDL
Author :
Adamec, Ing Filip ; Fryza, Ing Tomá
Author_Institution :
Dept. of Radio Electron., Brno Univ. of Technol., Brno, Czech Republic
Abstract :
This article describes a basic algorithm for a division operation. Its performance and consideration of the implementation in VHDL are discussed. There are described three possible implementations, the maximum performance in FPGAs, e.g. propagation delays and number of necessary steps to enumerate the correct result. In the conclusion the performance and necessary number of steps are compared.
Keywords :
delays; field programmable gate arrays; hardware description languages; FPGAs; VHDL; binary division algorithm; division operation; propagation delays; Clocks; Educational institutions; Field programmable gate arrays; Hardware; Microprocessors; Pipelines; Propagation delay; Division operation; FPGA; VHDL; implementation;
Conference_Titel :
Radioelektronika, 2009. RADIOELEKTRONIKA '09. 19th International Conference
Conference_Location :
Bratislava
Print_ISBN :
978-1-4244-3537-1
Electronic_ISBN :
978-1-4244-3538-8
DOI :
10.1109/RADIOELEK.2009.5158757
