DocumentCode
2444378
Title
Carry Estimation for Two´s Complement Fixed-Width Multipliers
Author
Liao, Yen-Chin ; Chang, Hsie-Chia ; Liu, Chih-Wei
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu
fYear
2006
fDate
Oct. 2006
Firstpage
345
Lastpage
350
Abstract
An n-bit fixed-width multiplier keeps the input-width and output-width the same by truncating the n least significant output bits. In order to reduce the complexity, direct-truncation multipliers omit the half of the partial products corresponding to the truncated part. However, a large truncation error will be introduced. Thus, error compensation, which equals to estimating the carry bits, is required. In this paper, three carry estimation schemes based on the dependency among the partial products and the inputs are proposed. Not only this dependency is investigated, statistical analysis for these estimation approaches is provided. Applying the proposed schemes, at least 84% the truncation error can be reduced
Keywords
carry logic; multiplying circuits; statistical analysis; carry estimation; statistical analysis; two´s complement fixed-width multiplier; Digital filters; Digital signal processing; Equations; Error analysis; Error compensation; Fast Fourier transforms; Filtering; Finite wordlength effects; Statistical analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems Design and Implementation, 2006. SIPS '06. IEEE Workshop on
Conference_Location
Banff, Alta.
ISSN
1520-6130
Print_ISBN
1-4244-0383-9
Electronic_ISBN
1520-6130
Type
conf
DOI
10.1109/SIPS.2006.352606
Filename
4161876
Link To Document