An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC Encoder

Author

Rahman, Choudhury A. ; Badawy, Wael

Author_Institution

Lab. for Integrated Video Syst., Calgary Univ., Alta.

fYear

2006

fDate

Oct. 2006

Firstpage

368

Lastpage

371

Abstract

This paper presents a novel context-based adaptive variable length coding (CAVLC) architecture based on split and shared VLC look up table technique. The architecture is prototyped in Verilog HDL, simulated and synthesized for Xilinx Virtex II FPGA. The experimental result shows that the proposed architecture is capable of processing CIF frame sequences in real-time and is smaller than any of the real-time architectures proposed so far. The maximum speed of the core is around 60 MHz

Keywords

field programmable gate arrays; hardware description languages; table lookup; variable length codes; video coding; CAVLC IP-block; CIF frame sequences processing; H.264-AVC encoder; Verilog HDL; Xilinx Virtex II FPGA; context-based adaptive variable length coding; look up table technique; real-time architecture; Automatic voltage control; Digital multimedia broadcasting; Entropy coding; Hardware design languages; IEC standards; ISO standards; Optical devices; Real time systems; Streaming media; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems Design and Implementation, 2006. SIPS '06. IEEE Workshop on

Conference_Location

Banff, Alta.

ISSN

1520-6130

Print_ISBN

1-4244-0383-9

Electronic_ISBN

1520-6130

Type

conf

DOI

10.1109/SIPS.2006.352610

Filename

4161880