An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC Encoder

This paper presents a novel context-based adaptive variable length coding (CAVLC) architecture based on split and shared VLC look up table technique. The architecture is prototyped in Verilog HDL, simulated and synthesized for Xilinx Virtex II FPGA. The experimental result shows that the proposed architecture is capable of processing CIF frame sequences in real-time and is smaller than any of the real-time architectures proposed so far. The maximum speed of the core is around 60 MHz