Pipeline Architecture of Particle Swarm Optimization

Author

Cai, Xiao ; Ngah, Syahrulanuar ; Zhu, Hui ; Tanabe, Yuji ; Baba, Takaaki

Author_Institution

Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan

fYear

2010

fDate

18-20 Aug. 2010

Firstpage

3

Lastpage

8

Abstract

This paper develops pipeline architecture of particle swarm optimization with random time-varying inertia weight and acceleration coefficients (PSO-RTVIWAC) based on existing serial architecture. The proposed architecture incorporated two features to reduce calculation error and keep high speed calculation with acceptable chip area cost. First, actual hardware design is simplified. Then the pipeline mechanism is introduced. The developed system is implemented in field programmable gate array (FPGA) and achieves high stability with slightly increased speed.

Keywords

field programmable gate arrays; parallel architectures; particle swarm optimisation; pipeline processing; chip area cost; field programmable gate array; high speed calculation; particle swarm optimization; pipeline architecture; random time varying acceleration coefficient; random time varying inertia weight coefficient; reduce calculation error; Computer architecture; Hardware; Mathematical model; Pipelines; Random access memory; Real time systems; Registers; field programmable gate array; particle swarm optimization; pipeline; positioning system;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Information Science (ICIS), 2010 IEEE/ACIS 9th International Conference on

Conference_Location

Yamagata

Print_ISBN

978-1-4244-8198-9

Type

conf

DOI

10.1109/ICIS.2010.42

Filename

5593142