Power bus optimal sizing in presence of power supply noise

As a consequence of the growing complexity in ultra deep submicron designs, phenomena like IR drops, electromigration and ground bounce are assuming increasing proportions in high performance integrated circuits, compromising their performances and their functionality. This paper suggests a methodology to evaluate power supply noise generation while optimizing power supply bus sizes. Its appropriateness seems to be helpful if applied during the circuit design flow in conjunction with a project tool having as a preeminent target noise reduction.