An area-efficient symbol deinterleaver architecture for DVB-T

A new architecture has been proposed for the symbol deinterleaver used in DVB-T channel decoder. In conventional architecture of the symbol deinterleaver two separate single-port RAMs have been used for buffering odd and even OFDM symbols. In this paper we show that these two RAMs can be merged so that only one single-port RAM for buffering of both odd and even symbols would be used and hence the required memory space will be reduced by half. Also, an architecture for address generator has been designed for generating consecutive valid addresses. Due to the simplicity of the proposed architecture, it can be easily implemented; however, the operation clock-frequency doubled with respect to the conventional two-RAM architecture.