Title :
High level analysis of trade-offs across different partitioning schemes for wireless applications
Author :
Agrawal, P. ; Fasthuber, R. ; Raghavan, P. ; Vander Aa, T. ; Ahmad, U. ; Van der Perre, L. ; Catthoor, F.
Author_Institution :
SSET, IMEC, Leuven, Belgium
Abstract :
With the advent of heterogeneous MPSoC (Multi-Processors System-on-Chip) implementations of wireless applications, system partitioning and mapping has become a key challenge. To achieve efficient designs, system partitioning should simultaneously consider application characteristics, architecture constraints and physical design costs. It is also important to analyze the impact of partitioning on the system´s area, energy and performance, as early as possible in the design flow. In this paper, we analyze the impact of different partitioning schemes for lattice reduction based MIMO detector. We show the trade-offs due to different partitioning schemes on area, energy and data parallelization factor for a given performance target for different number of processors. We carry out analysis based on high level estimates derived from the application and a set of characterized datapath and memory primitives for a template based architecture.
Keywords :
MIMO communication; system-on-chip; MIMO detector; data parallelization factor; datapath characterization; design flow; heterogeneous MPSoC implementations; high-level analysis; lattice reduction; memory primitives; multiprocessor system-on-chip; partitioning schemes; system mapping; system partitioning; template-based architecture; wireless applications; Complexity theory; Computer architecture; Detectors; Kernel; MIMO; Program processors; Radio frequency; Complexity Analysis; MIMO; MP-SoC; Partitioning;
Conference_Titel :
Signal Processing Systems (SiPS), 2011 IEEE Workshop on
Conference_Location :
Beirut
Print_ISBN :
978-1-4577-1920-2
DOI :
10.1109/SiPS.2011.6088967