Efficient multiplierless architecture for frame synchronization in DVB-S2 standard

The first challenging step of the demodulation of the DVB-S2 signal with function of VCM (Variable Coding and Modulation)/ACM (Adaptive Coding and Modulation) is the detection of the Physical Layer (PL) header. PL header is transmitted using π/2-BPSK modulation and is composed of a fixed part (26 bits of Start Of Frame (SOF)) and a variable part (64 bits codeword of PL Signaling (PLS) code that defines the structure of the PL frame). Since the 90 bits corresponding to the PL header are affected by noise, the carrier frequency offset and the phase noise, the synchronization task in a DVB-S2 receiver is thus a critical task. In this paper, we present a properties of the Hadamard code used to encode the information of the PLS code to reinforce frame detection before knowing the actual value of the PL code. Moreover, we propose to perform the computation in the polar domain in order to avoid the need of multiplier and thus, to obtain a very low cost implementation. The associated decoder architecture is presented together with the measured performance at several SNRs.