DocumentCode :
2444741
Title :
Hardware efficiency versus error probability in unreliable computation
Author :
Tang, Yangyang ; Boutillon, Emmanuel ; Jégo, Christophe ; Jézéquel, Michel
Author_Institution :
Lab.-STICC, Univ. de Bretagne Sud, Lorient, France
fYear :
2011
fDate :
4-7 Oct. 2011
Firstpage :
168
Lastpage :
173
Abstract :
For the purpose of mitigating the effect of transient error in unreliable architecture, many authors have proposed redundant computation (sensitive to error) and an error-free correction unit. In this paper, taking into account that the correction unit is also subject to error, we propose to evaluate the quality of an architecture using not only its efficiency (i.e. the normalized number of operation per area and per unit of time), but also its final output error rate. The new criteria, namely Reliability-Efficiency Criteria (RE-Criteria) thus defines a two dimensional space of solution, i.e. a Pareto distribution [1]. After revisiting well-known correcting techniques with the RE-Criteria, we give an example of Pareto distribution based on a classical FIR filter performed with the error-correcting mechanism based architectures.
Keywords :
FIR filters; Pareto distribution; circuit reliability; electronic engineering computing; error correction; error statistics; redundancy; FIR filter; Pareto distribution; RE-criteria; error correcting mechanism; error free correction unit; error probability; hardware efficiency; redundant computation; reliability efficiency; unreliable architecture; Clocks; Computer architecture; Decoding; Error probability; Finite impulse response filter; Reliability; Error Probability; FIR Filter; Hardware Efficiency; RNS; Reliable Computation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems (SiPS), 2011 IEEE Workshop on
Conference_Location :
Beirut
ISSN :
2162-3562
Print_ISBN :
978-1-4577-1920-2
Type :
conf
DOI :
10.1109/SiPS.2011.6088969
Filename :
6088969
Link To Document :
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