DocumentCode :
2444742
Title :
A polynomial division pipelined architecture for CRC error detecting codes
Author :
Monteiro, Fabrice ; Dandache, A. ; M´Sir, A. ; Lepley, Bernard
Author_Institution :
LICM, Metz Univ., France
fYear :
2001
fDate :
29-31 Oct. 2001
Firstpage :
133
Lastpage :
136
Abstract :
Error detection in telecommunication applications is frequently ensured with CRC (Cyclic Redundancy Checking). However, the evolution towards increasing data rates increases the need for more and more sophisticated implementations. In this paper, we present an effective architecture for the CRC function based on a pipelined implementation of the polynomial division. It improves very effectively the speed performance, allowing data rates from 1 Gbit/s to 4 Gbit/s on FPGA implementations, according to the parallelisation level (8 to 32 bit).
Keywords :
error detection codes; field programmable gate arrays; parallel architectures; pipeline processing; polynomials; redundancy; telecommunication computing; 1 to 4 Gbit/s; 8 to 32 bit; CRC error detecting codes; FLEX10KE ALTERA FPGA; FPGA implementations; cyclic redundancy checking; parallelisation level; polynomial division pipelined architecture; speed performance improvement; telecommunication applications; Circuits; Clocks; Cyclic redundancy check; Cyclic redundancy check codes; Field programmable gate arrays; Frequency; Pipeline processing; Polynomials; Protocols; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics, 2001. ICM 2001 Proceedings. The 13th International Conference on
Print_ISBN :
0-7803-7522-X
Type :
conf
DOI :
10.1109/ICM.2001.997505
Filename :
997505
Link To Document :
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