DocumentCode
2444774
Title
A hardware accelerator for DSP system design: University of Tehran DSP Hardware Emulator (UTDHE)
Author
Mahdiany, H.R. ; Hormati, A. ; Fakhraie, S.M.
Author_Institution
ECE Dept., Tehran Univ., Iran
fYear
2001
fDate
29-31 Oct. 2001
Firstpage
141
Lastpage
144
Abstract
DSP systems play an important role in modern industry and new DSP systems should be designed rapidly to overcome the new necessities that arise. However, the process of designing a DSP system is very time consuming and most of this time is wasted on simulating and debugging of such complex systems. We have designed and implemented a system that makes it possible to emulate and debug large DSP designs (up to 250,000 gates) as fast as possible. With this system, the user can test his or her DSP scheme with fast hardware emulation instead of slow software simulation and as a result reduce time to market significantly. The designed DSP HWE system can emulate complex DSPs that operate at different clock rates and need up to four modules of external memories. It is important to note that low-level simulation of such systems needs a long simulation time, making it impossible to completely simulate and test such designs. As a result of this work, such prohibitive factor has been eliminated.
Keywords
VLSI; circuit analysis computing; computer debugging; digital signal processing chips; field programmable gate arrays; virtual machines; DSP system design; FLEX10K250 FPGA; RAM based FPGA; UTDHE; University of Tehran DSP hardware emulator; complex DSPs; hardware accelerator; Digital signal processing; Emulation; Field programmable gate arrays; Hardware; Pins; Random access memory; Read-write memory; Software testing; System testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2001. ICM 2001 Proceedings. The 13th International Conference on
Print_ISBN
0-7803-7522-X
Type
conf
DOI
10.1109/ICM.2001.997507
Filename
997507
Link To Document