Clock qualification algorithm for timing analysis of custom CMOS VLSI circuits with overlapped clocking disciplines and on-section clock derivation

A fast clock qualification scheme for the timing analysis of custom CMOS VLSI circuits is presented. Clocking disciplines that encompass both nonoverlapped and overlapped clocks are considered under this scheme. On-section clock derivation to derive single-phase clocks locally from two or more overlapped clocks is considered. A given clock cycle is essentially split into logical time segments during which state transitions occur in the design. For each of these time segments, clock stamps are evaluated and propagated down the clock path. An event-driven approach is employed for clock stamp evaluation and propagation. This provides the requisite flexibility for analyzing multiple levels of clock derivation in any clock path