DocumentCode
2444994
Title
Single Event Gate Rupture Testing on 90 nm Bulk CMOS Deep Trench Oxide Capacitors
Author
Lawrence, Reed K. ; Zimmerman, Jeffery A. ; Ross, Jason F.
Author_Institution
BAE Syst., Manassas, VA, USA
fYear
2009
fDate
20-24 July 2009
Firstpage
71
Lastpage
75
Abstract
Single event gate rupture (SEGR) testing on a deep trench oxide capacitor used for the reduction of single event upsets (SEU) in a 90 nm bulk complementary metal oxide semiconductor (CMOS) technology indicates that SEGR was not detected.
Keywords
CMOS integrated circuits; MOS capacitors; fracture; integrated circuit testing; ion beam effects; radiation hardening (electronics); semiconductor device testing; SEGR test; bulk CMOS deep trench oxide capacitor; complementary metal oxide semiconductor technology; ion beam radiation effect; radiation hardening; single event gate rupture testing; single event upsets; size 90 nm; Breakdown voltage; CMOS technology; Capacitors; Damping; Degradation; Random access memory; Semiconductor device testing; Silicon; Single event upset; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Radiation Effects Data Workshop, 2009 IEEE
Conference_Location
Quebec City, QC
Print_ISBN
978-1-4244-5092-3
Type
conf
DOI
10.1109/REDW.2009.5336310
Filename
5336310
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