• DocumentCode
    244593
  • Title

    Dynamic quadrant partitioning adaptive routing algorithm for irregular reduced vertical link density topology 3-Dimensional Network-on-Chips

  • Author

    Haoyuan Ying ; Hofmann, Klaus ; Hollstein, Thomas

  • Author_Institution
    Integrated Electron. Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany
  • fYear
    2014
  • fDate
    21-25 July 2014
  • Firstpage
    516
  • Lastpage
    522
  • Abstract
    3-Dimensional Networks-on-Chips (3D NoCs) are proposed as the next generation interconnect infrastructure for multi/many core embedded systems due to the high performance characteristics and scalability. However the heat and thermal issues in 3D NoCs are critical. Reducing the vertical links between dies becomes can be one of the proper solutions, but the 3D NoC system performance can be harmed due to the less number of possible vertical links. In order to find the best trade-off point between the vertical links reduction and 3D NoC performance, in this paper, we demonstrate a dynamic quadrant partitioning (DQP) adaptive routing algorithm for 3D NoCs with irregular reduced vertical link density topologies, which can improve the system performance (latency max. 10.9% and energy max. 24.1%) in comparison to deterministic routing algorithm with the same vertical link number configurations. Also our DQP routing algorithm can maintain the system performance in comparison to full vertical link connection running dimension-order deterministic routing algorithm (ZXY) by reducing 40% vertical links number. The comparison results are demonstrated with different benchmark applications and random generated task graphs.
  • Keywords
    network routing; network-on-chip; power aware computing; 3-dimensional network-on-chips; 3D NoC; NoC heat issue; NoC thermal issue; dimension-order deterministic routing algorithm; dynamic quadrant partitioning adaptive routing algorithm; irregular reduced vertical link density topology; many core embedded systems; multicore embedded systems; next generation interconnect infrastructure; random generated task graphs; vertical link number configurations; Heuristic algorithms; Partitioning algorithms; Ports (Computers); Routing; System recovery; Table lookup; Three-dimensional displays; 3D NoC; Adaptivity; Irregular Topology; Routing Algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing & Simulation (HPCS), 2014 International Conference on
  • Conference_Location
    Bologna
  • Print_ISBN
    978-1-4799-5312-7
  • Type

    conf

  • DOI
    10.1109/HPCSim.2014.6903729
  • Filename
    6903729