An area-efficient standard-cell floating-point unit design for a processing-in-memory system

The data-intensive architecture (DIVA) system incorporates processing-in-memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth-limited applications. One of the key capabilities of this architecture is wideword floating-point computation, which enables aggregate floating-point operations. Each PIM chip includes eight basic instructions and IEEE-754 compliant rounding and exceptions. Through pipeline scheduling and a hardware-efficient division algorithm, the resulting FPU is well-balanced between area and performance. This paper details the design and implementation of this FPU based on standard cell methodology in 0.18/spl mu/m CMOS technology. Area, power dissipation and performance are also discussed.