Analysis and validation of partially dynamically reconfigurable architecture based on Xilinx FPGAs

Partial dynamic reconfiguration of FPGAs is a methodology that allows the efficient use of an FPGAs resources and an improved degree of flexibility with respect to static hardware when designing an architecture on FPGA. However, due to the number of technology dependent constraints to be satisfied and to the lack of a complete automatize design flow, which implies that several manual operations still need to be done in the respect of those constraints, the design of a partial dynamic reconfigurable system can be seen as a complex task to be accomplished. We introduce a methodology for the low level configuration analysis and for the debugging and validation of the bitstream files of architectures exploiting dynamic partial reconfiguration on Xilinx FPGAs. The proposed methodology has been validated using different Xilinx FPGAs Spartan 3, Virtex II Pro and Virtex 4. The methodology has subsequently yielded a framework in which the validation and debugging techniques have been implemented. The framework, called Rebit, supports the designer in validating a partial dynamic reconfigurable architecture, debugging the user-defined constraints for the reconfigurable regions of the design and validating partial bitstream occupation data against those defined reconfigurable regions.