A 12b 320 MSample/s current-steering CMOS D/A converter in 0.44mm/sup 2/

Author

O´Sullivan, Kevin ; Gorman, Chris ; Hennessy, Michael ; Callaghan, Vincent

Author_Institution

Silicon & Software Syst., Dublin, Ireland

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

89

Lastpage

92

Abstract

This paper presents a 12-bit 320MSample/s current-steering D/A converter in 0.18/spl mu/m CMOS. In order to achieve high linearity and SFDR a large degree of segmentation has been used. A ´design for layout´ approach has allowed this to be done in an area of just 0.44mm/sup 2/ . The increased switching noise associated with a high degree of segmentation has been reduced by new latch architecture. DNL of /spl plusmn/0.4 LSB and INL of /spl plusmn/ 0.5 LSB have been measured. SFDR of 95 dB has been achieved. The validity of the techniques used has been proven by fabricating the converter in 2 separate 0.18/spl mu/m processes with similar results measured for both.

Keywords

CMOS integrated circuits; digital-analogue conversion; integrated circuit layout; 0.18 microns; current-steering CMOS; design for layout approach; digital-to-analogue converter; increased switching noise; latch architecture; Decoding; Delay; Frequency synchronization; Impedance; Latches; Linearity; Signal synthesis; Silicon; Software systems; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257079

Filename

1257079