A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design

Author

Yamaoka, Hiroaki ; Ikeda, Makoto ; Asada, Kunihiro

Author_Institution

Dept. of Electron. Eng., Tokyo Univ., Japan

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

189

Lastpage

192

Abstract

This paper presents a new high-speed logic circuit family based on an interdigitated array structure for deep sub-micron IC design. The circuit family consists of a comparator, a priority encoder, and an incrementor for 128-bit data processing. The proposed circuit includes three schemes: 1) a divided column scheme, 2) a programmable sense-amplifier activation scheme, and 3) an interdigitated column scheme. These schemes achieved a 22.2% delay reduction and a 37.5% chip area reduction over the conventional high-speed array logic circuit in a 0.13-/spl mu/m CMOS technology with a supply voltage of 1.2 V. A module generator of the logic circuit family was also developed to enhance the process portability for IP-based design.

Keywords

CMOS logic circuits; comparators (circuits); encoding; integrated circuit design; integrated logic circuits; logic design; 0.13 microns; 1.2 V; CMOS technology; IP-based design; chip area reduction; comparator; data processing; deep sub-micron IC design; delay reduction; divided column scheme; high-speed array logic circuit; high-speed logic circuit family; incrementor; interdigitated array structure; interdigitated column scheme; module generator; priority encoder; process portability; programmable sense-amplifier activation scheme; CMOS logic circuits; CMOS process; CMOS technology; Data processing; Delay; High speed integrated circuits; Logic arrays; Logic circuits; Programmable logic arrays; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257104

Filename

1257104