DocumentCode
2446812
Title
VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR
Author
Wang, Yanhua ; Zhou, Qiang ; Bian, Jinian ; Qu, Junhua
Author_Institution
North China Electr. Power Univ., Beijing
fYear
2007
fDate
15-18 Oct. 2007
Firstpage
349
Lastpage
354
Abstract
VPH (versatile placer for hierarchical FPGAs, HFPGAs) is a place tool aiming at a routability-driven placement process for HFPGAs. It improves the placement algorithm of VPR (versatile place and route) by taking into consideration of specific constraints of hierarchical architectures for HFPGAs, and updates the place process based on it. Further more, thanks to the interconnect predictability, VPH can take into account routing constraints in early placement stage and evaluate efficiently the routability of the circuit. In this paper, we introduce the VPH design framework and its related placement algorithms. Its effectiveness is validated by the experimental results of MCNC benchmark.
Keywords
field programmable gate arrays; VPR; versatile place and route; versatile placer for hierarchical FPGA; Circuit topology; Computer science; Costs; Field programmable gate arrays; Integrated circuit interconnections; Logic devices; Reconfigurable logic; Routing; Switches; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design and Computer Graphics, 2007 10th IEEE International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-1579-3
Electronic_ISBN
978-1-4244-1579-3
Type
conf
DOI
10.1109/CADCG.2007.4407907
Filename
4407907
Link To Document