DocumentCode
2446882
Title
A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-/spl mu/m CMOS
Author
Zjajo, Amir ; Van der Ploeg, Hendrik ; Vertregt, Maarten
Author_Institution
Philips Res. Labs., Eindhoven, Netherlands
fYear
2003
fDate
16-18 Sept. 2003
Firstpage
241
Lastpage
244
Abstract
The design, optimisation, efficiency and measurement results of the two-step 12-bits analogue-to-digital converter fabricated in a 0.18-/spl mu/m CMOS process are presented. Performance of 66.3dB SNR, -73.1dB THD, 78.4dB SFDR, 10.5 ENOB at 60 MS/s and 9.7 ENOB at 80 MS/s has been obtained using a mixed-signal chopping and calibration algorithm, drawing less than 100 mW from 1.8V supply for both analogue and digital core. The ADC has been fabricated in a single-poly 5-metal 0.18-/spl mu/m CMOS process and measures 0.67 mm/sup 2/.
Keywords
CMOS integrated circuits; analogue-digital conversion; optimisation; 0.18 microns; 1.8 V; 100 mW; analogue core; analogue-to-digital converter; calibration algorithm; digital core; mixed-signal chopping; single-poly 5-metal CMOS process; two-step ADC; CMOS technology; Circuits; Dynamic range; Dynamic voltage scaling; Power amplifiers; Quantization; Resistors; Signal processing; Signal to noise ratio; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location
Estoril, Portugal
Print_ISBN
0-7803-7995-0
Type
conf
DOI
10.1109/ESSCIRC.2003.1257117
Filename
1257117
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