Aggressor aware repeater circuits for improving on-chip bus performance and robustness

As the technology scales, on-chip interconnects are becoming more and more narrow while their height is not scaling linearly with their width making their aspect ratios larger. This leads to an increase of coupling capacitance with neighbouring wires, leading to higher crosstalk. Combined with a higher wire resistance this leads to poor performance due to a slow RC response at the receiving end of the wire. This scenario is further degraded when neighbouring wires switch in opposite directions with respect to the victim wire. We propose a novel aggressor aware repeater, which, according to the state of neighbouring wires in an on-chip bus changes its switching threshold to achieve higher performance and higher robustness. The switching threshold of the repeater is lowered in states where worst-case switching can occur. This reduces propagation delay. It can also be raised when worst-case noise can occur (which can cause a glitch) to ensure higher noise immunity. This paper presents the design of aggressor aware repeaters for high performance buses. Simulation results for a 10mm long bus in 0.13/spl mu/m technology, show an improvement of 28.8% in speed and 41.1% in power-delay as stated in T. Iima et al. (1995).