Title :
10 Gb/s CMOS limiting amplifier for optical links
Author :
Tao, Rui ; Berroth, Manfred
Author_Institution :
Inst. of Electr. & Opt. Commun. Eng., Stuttgart Univ., Germany
Abstract :
A 10 Gb/s limiting amplifier was designed, fabricated and tested using an industrial digital 0.18 /spl mu/m CMOS process. The parallel feedback circuit topology is adopted to broaden the bandwidth. With the supply voltage of 2.4 V, this limiting amplifier can operate at 10 Gb/s at a dynamic range from 25 mV up to 250 mV. The power consumption is 120 mW.
Keywords :
CMOS digital integrated circuits; amplifiers; feedback; optical limiters; optical links; 0.18 microns; 10 Gbit/s; 120 mW; 2.4 V; 25 to 250 mV; CMOS limiting amplifier; digital CMOS process; optical links; parallel feedback circuit topology; Bandwidth; CMOS process; Circuit testing; Circuit topology; Electricity supply industry; Feedback circuits; Optical amplifiers; Optical fiber communication; Semiconductor optical amplifiers; Textile industry;
Conference_Titel :
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7995-0
DOI :
10.1109/ESSCIRC.2003.1257128
