DocumentCode
2447290
Title
Power-performance optimal 64-bit carry-lookahead adders
Author
Zlatanovici, Radu ; Nikolic, Borivoje
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
2003
fDate
16-18 Sept. 2003
Firstpage
321
Lastpage
324
Abstract
A circuit sizing tool that minimizes the delay under energy constraints has been developed using optimisation software, tabulated delay models and analytical energy models. The tool is used to generate energy-delay (E-D) tradeoff curves for selected high-performance 64-bit carry-lookahead adders. The optimisation indicates that the sparse radix-4 carry-lookahead adder with sparseness factor of 2 has optimal performance in the energy-delay space.
Keywords
adders; circuit optimisation; delays; 64 bit; analytical energy models; circuit sizing tool; delay minimization; energy constraints; energy-delay space; energy-delay tradeoff curves; optimal performance; optimisation software; performance optimal carry-lookahead adders; power optimal carry-lookahead adders; sparse radix-4 carry-lookahead adder; tabulated delay models; Adders; Analytical models; Circuits; Concurrent computing; Constraint optimization; Delay; Equations; Logic; Topology; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location
Estoril, Portugal
Print_ISBN
0-7803-7995-0
Type
conf
DOI
10.1109/ESSCIRC.2003.1257137
Filename
1257137
Link To Document