Title :
A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-/spl mu/m SOI CMOS technology
Author :
Plouchart, Jean-Olivier ; Kim, Jonghae ; Zamdmer, Noah ; Sherony, Melanie ; Tan, Yue ; Yoon, Meeyoung ; Talbi, Mohamed ; Ray, Asit ; Wagner, Lawrence
Author_Institution :
IBM Semicond. R&D Center, Hopewell Junction, NY, USA
Abstract :
This paper presents a three-stage CML (current mode logic) ring VCO fabricated in a 0.12 /spl mu/m SOI CMOS technology with a minimum stage delay of 5.4 ps at a differential voltage swing of 400 mV. The maximum oscillation frequency measured is 31 GHz. A tuning range as high as 10% is measured. The phase noise is -95.6 dBc at an offset frequency of 10 MHz. The energy per stage is as low as 26.8 fJ at a power supply voltage of 1.5V and a delay per stage of 5.95 ps.
Keywords :
CMOS integrated circuits; current-mode logic; delay circuits; phase noise; silicon-on-insulator; voltage-controlled oscillators; 0.12 microns; 1.5 V; 10 MHz; 26.8 fJ; 31 GHz; 400 mV; 5.4 ps; 5.95 ps; CML ring VCO; SOI CMOS technology; current mode logic; differential voltage swing; minimum stage delay; phase noise; three-stage CML; CMOS technology; Circuits; Clocks; Delay; Frequency; Parasitic capacitance; Power supplies; Tail; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7995-0
DOI :
10.1109/ESSCIRC.2003.1257146
