Title :
Implementation of the compression function for selected SHA-3 candidates on FPGA
Author :
Namin, A.H. ; Hasan, M.A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada
Abstract :
Implementation of the main building block (compression function) for five different SHA-3 candidates on reconfigurable hardware is presented. The five candidates, namely Blue Midnight Wish, Luffa, Skein, Shabal, and Blake have been considered since they present faster software implementation results compared to the rest of the SHA-3 proposals. The results allow an easy comparison for hardware performance of the candidates.
Keywords :
field programmable gate arrays; reconfigurable architectures; FPGA; compression function implementation; hardware performance; reconfigurable hardware; selected SHA-3 candidates; software implementation; Ash; Combinational circuits; Data preprocessing; Field programmable gate arrays; Frequency; Hardware; Iterative algorithms; NIST; Proposals; Software packages; Compression Function; FPGA; Hash; SHA-3;
Conference_Titel :
Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
978-1-4244-6533-0
DOI :
10.1109/IPDPSW.2010.5470742
