A 6.25Gbps Feed-forward Equalizer in 0.18μm CMOS Technology for SerDes

Author

Jian Gao ; Qing-Sheng Hu

Author_Institution

Inst. of RF- & OE-ICs, Southeast Univ., Nanjing, China

fYear

2012

fDate

25-27 Oct. 2012

Firstpage

1

Lastpage

4

Abstract

This paper presents a 6.25Gbps feed-forward equalizer (FFE) to reduce the inter-symbol-interference (ISI) in high-speed transmission backplane. The 3-tap fractionally spaced equalizer consists of a delay line, multiplier & summer cells and an output circuit. Active-inductive peaking circuit and capacitor-degenerated circuit are used in the delay line and the output stage respectively to meet the bandwidth demand. The proposed FFE has been implemented in TSMC 0.18μm CMOS technology with a whole area of 0.5mm×0.51mm including I/O pads. The power consumption of the core circuit is 31.7mW under 1.8V power supply. Post simulation results show that the distorted signal through a 24-inch backplane is well recovered by this equalizer.

Keywords

CMOS integrated circuits; capacitors; delay lines; equalisers; feedforward; inductors; intersymbol interference; multiplying circuits; 3-tap fractionally spaced equalizer; FFE; I-O pad; ISI; SerDes; TSMC CMOS technology; active-inductive peaking circuit; bit rate 6.25 Gbit/s; capacitor-degenerated circuit; delay line; feedforward equalizer; high-speed transmission backplane; intersymbol-interference reduction; multiplier; power 31.7 mW; power consumption; serializer-deserializer; size 0.18 mum; size 24 inch; summer cell; voltage 1.8 V; active-inductive peaking; capacitor-degenerated; current mode logic (CML); delay line cell; feed-forward equalizer (FFE); fractionally spaced equalizer (FSE);

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications & Signal Processing (WCSP), 2012 International Conference on

Conference_Location

Huangshan

Print_ISBN

978-1-4673-5830-9

Electronic_ISBN

978-1-4673-5829-3

Type

conf

DOI

10.1109/WCSP.2012.6543018

Filename

6543018