Title :
Dynamic biasing: a low power linearisation technique
Author :
Coppejans, Philippe ; Steyaert, Michiel
Author_Institution :
ESAT-MICAS, KU Leuven, Belgium
Abstract :
A highly linear opamp processed in a 0.25/spl mu/m 2 V CMOS technology suitable for an intermediate frequency (IF) continuous time sigma-delta analog-to-digital converter (/spl Sigma//spl Delta/ ADC) is presented. Due to an improved technique, called dynamic biasing, distortion components in an IF band, typically situated at frequencies from 1 to 10 MHz for a low-IF receiver architecture, are lowered without any signal degeneration. The circuit achieves an IIP3 and an IIP5 of more than 20 dBm. The power consumption is limited to 3.4 mW.
Keywords :
CMOS integrated circuits; continuous time systems; linearisation techniques; low-power electronics; operational amplifiers; sigma-delta modulation; 0.25 microns; 1 to 10 MHz; 2 V; 3.4 mW; CMOS technology; continuous time ADC; dynamic biasing; intermediate frequency ADC; linear opamp; low power linearisation technique; low-IF receiver architecture; sigma-delta analog-to-digital converter; signal degeneration; Analog-digital conversion; CMOS technology; Degradation; Distortion; Dynamic range; Energy consumption; Filters; Linearity; Linearization techniques; Resistors;
Conference_Titel :
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7995-0
DOI :
10.1109/ESSCIRC.2003.1257149
