High performance multilevel systolic fuzzy inference unit

A novel high-perfomance fuzzy inference unit is presented. The design is based on techniques of digital systolic array structures. It allows a very high through-output independent from the number of antecedents, consecuents, number of labels per variable and bits of encoding. It allows a very good number of rules without loss of efficiency. The design has been done in VHDL and allows the automatic circuit configuration for any number of antecedents, consecuents, bits of encoding and number of rules. The circuit simulation has been carried out by using ES2 1 μm standards cells, and its results has given a performance over 10 MFLIPS