High performance multilevel systolic fuzzy inference unit

Author

de Salvador, L. ; Gutierrez, Julio

Author_Institution

Hardware & Adv. Control Lab., Nat. Inst. of Aerosp. Technol., Madrid, Spain

fYear

1994

fDate

18-21 Dec 1994

Firstpage

127

Lastpage

131

Abstract

A novel high-perfomance fuzzy inference unit is presented. The design is based on techniques of digital systolic array structures. It allows a very high through-output independent from the number of antecedents, consecuents, number of labels per variable and bits of encoding. It allows a very good number of rules without loss of efficiency. The design has been done in VHDL and allows the automatic circuit configuration for any number of antecedents, consecuents, bits of encoding and number of rules. The circuit simulation has been carried out by using ES2 1 μm standards cells, and its results has given a performance over 10 MFLIPS

Keywords

fuzzy logic; hardware description languages; inference mechanisms; logic CAD; systolic arrays; 10 MFLIPS; VHDL; automatic circuit configuration; circuit simulation; digital systolic array structures; fuzzy inference unit; high-perfomance; performance; Computer architecture; Fuzzy logic; Fuzzy systems; Laboratories; Pipelines; Silicon; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Fuzzy Information Processing Society Biannual Conference, 1994. Industrial Fuzzy Control and Intelligent Systems Conference, and the NASA Joint Technology Workshop on Neural Networks and Fuzzy Logic,

Conference_Location

San Antonio, TX

Print_ISBN

0-7803-2125-1

Type

conf

DOI

10.1109/IJCF.1994.375138

Filename

375138