A new area-power efficient split-output TSPC CMOS latch for high-speed VLSI applications

Author

Pontikakis, Bill ; Nekili, Mohaiiied

Author_Institution

Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

fYear

2001

fDate

29-31 Oct. 2001

Firstpage

213

Lastpage

216

Abstract

In this paper, a new True Single-Phase clocked (TSPC) split-output latch is introduced, and compared with existing split-output latches. The comparison is based on the criteria of robustness, area and power efficiency at high speeds. SPICE simulation is used with a 0.5-μm CMOS process, to compare four different P-MOS split-output latches at 625 MHz, using a 3.3 V power supply. It is shown that the new split-output latch is more area-power efficient, and significantly more robust, than the existing split-output CMOS latches.

Keywords

CMOS logic circuits; SPICE; VLSI; circuit simulation; clocks; flip-flops; high-speed integrated circuits; logic simulation; sequential circuits; 0.5 micron; 3.3 V; 625 MHz; SPICE simulation; area efficiency; area-power efficient circuit; high-speed VLSI applications; power efficiency; robust; robustness; split-output TSPC CMOS latch; true single-phase clocked latch; Application software; Batteries; Circuits; Clocks; Latches; Power supplies; Robustness; SPICE; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2001. ICM 2001 Proceedings. The 13th International Conference on

Print_ISBN

0-7803-7522-X

Type

conf

DOI

10.1109/ICM.2001.997648

Filename

997648