Title :
A 20 Gb/s 82mW one-stage 4:1 multiplexer in 0.13 /spl mu/m CMOS
Author :
Kehrer, Daniel ; Wohlmuth, Hans-Dieter
Author_Institution :
Infineon Technol. AG, Munich, Germany
Abstract :
A completely integrated 4:1 multiplexer for high speed operation and low power consumption in 0.13 /spl mu/m CMOS is presented. The circuit uses a new architecture where four data streams are multiplexed in one stage. Pulses with 25% duty cycle select inputs to appear at the MUX-output. The lower number of gates enables low power design. Relaxed timing conditions are additional benefits of the one-stage MUX topology. The MUX works from DC up to 20 Gb/s and consumes 82 mW.
Keywords :
CMOS integrated circuits; current-mode logic; logic gates; low-power electronics; multiplexing; multiplexing equipment; 0.13 microns; 20 Gbit/s; 82 mW; CMOS; circuit architecture; data streams; high speed operation; integrated multiplexer; low power consumption; low power design; one-stage multiplexer; relaxed timing conditions; CMOS logic circuits; Energy consumption; Inductors; Multiplexing; Pulse generation; Pulse inverters; Resistors; Timing; Topology; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7995-0
DOI :
10.1109/ESSCIRC.2003.1257153
