Abstract :
The introduction of very high deep sub-micron technology introduces a lot of new problems due to the increase in complexity. In order to handle huge chips containing 40-50 millions of transistors gathered in 30-40 blocks (commonly named IPs), multi clock domains, multi powered analog blocks, routed on 6 metal layers with some wire length measuring up to 3 cm, a hierarchical approach must be set up focusing on verification and timing closure. The author considers the following aspects of the problem: timing, data structures, top-down methodology, design teams, RTL quality, logic design standardization, DFT rules, formal proof, system verification, timing block level sign-off, and physical sign-off.
Keywords :
circuit layout CAD; design for testability; formal verification; integrated circuit layout; logic CAD; mixed analogue-digital integrated circuits; network routing; timing; CAD flow; DFT rules; IPs; RTL quality; data structures; design teams; formal proof; hierarchical approach; logic design standardization; metal layer routing; multi clock domains; multi powered analog blocks; physical sign-off; system on chip; system verification; timing; timing block level sign-off; top-down methodology; very high deep sub-micron technology; Clocks; Data structures; Design methodology; Length measurement; Logic design; Semiconductor device measurement; Standardization; System-on-a-chip; Timing; Wire;
