Bitline leakage equalization for sub-100nm caches

This paper describes a leakage-tolerant circuit technique for embedded sub-100nm SRAM´s. The proposed 8-transistor memory cells inject identical leakage currents into the differential bitlines. During a read operation, the active leakage-equalization eliminates the differential offset voltage due to leakage currents. This results in a fast differential voltage development in the input of sense amplifiers and therefore a faster read operation. The proposed technique significantly relaxes the conventional constraint on device I/sub ON//I/sub OFF/ ratio versus number of memory-cells per bitline. Consequently, a large number of leaky memory cells can share a single bitline eliminating the need for aggressive bitline partitioning. Up to 80% faster differential voltage development has been observed for 100nm 256-cells bitlines.