DocumentCode
2447725
Title
A novel hierarchical multi-port cache
Author
Zhu, Zhaomin ; Johguchi, Koh ; Mattausch, Hans Jürgen ; Koide, Tetsushi ; Hirakawa, Tai ; Hironaka, Tetsuo
Author_Institution
Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
fYear
2003
fDate
16-18 Sept. 2003
Firstpage
405
Lastpage
408
Abstract
A novel hierarchical multi-port cache is described in this paper, which implements the hierarchical multi-port memory architecture (HMA) based on 1-port banks. This type of cache has the advantages of high access bandwidth, low power dissipation and small area, which are studied and explained in detail. A test chip design of a 4-port HMA cache with 0.18/spl mu/m CMOS technology has been made.
Keywords
CMOS memory circuits; cache storage; integrated circuit testing; logic testing; memory architecture; 0.18 micron; 1-port banks; CMOS; HMA; hierarchical multiport memory architecture; high access bandwidth; low power dissipation; multiport cache; test chip design; Artificial intelligence; Bandwidth; CMOS technology; Chip scale packaging; Circuits; Data processing; Memory architecture; Multimedia systems; Power dissipation; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location
Estoril, Portugal
Print_ISBN
0-7803-7995-0
Type
conf
DOI
10.1109/ESSCIRC.2003.1257158
Filename
1257158
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